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rev. 1.1 4/01 copyright ? 2001 by silicon laboratories si4133g-ds11 si4133g si4123g/22g/13g/12g d ual -b and rf s ynthesizer w ith i ntegrated vco s f or gsm and gprs w ireless c ommunications features applications description the si4133g is a monolithic integrated circuit that performs both if and dual-band rf synthesis for gsm and gprs wireless communications applications. the si4133g includes three vcos, loop filters, reference and vco dividers, and phase detectors. divider and power down settings are programmable through a three-wire serial interface. functional block diagram dual-band rf synthesizers rf1: 900 mhz to 1.8 ghz rf2: 750 mhz to 1.5 ghz if synthesizer if: 500 mhz to 1000 mhz integrated vcos, loop filters, varactors, and resonators minimal external components required fast settling time: 140 s low phase noise programmable power down modes 1 a standby current 18 ma typical supply current 2.7 v to 3.6 v operation packages: 24-pin tssop and 28-pin mlp gsm, dcs1800, and pcs1900 cellular telephones gprs data terminals hscsd data terminals ifout ifla iflb rflc rfld rfla rflb rfout xin pwdnb sdata sclk senb if rf2 rf1 65 auxout n n n phase detector phase detector phase detector 22-bit data register serial interface power down control reference amplifier test mux patents pending ordering information: see page 28. pin assignments si4133g-bt si4133g-bm si4133g-bt sclk sdata gndr rfld rflc gndr rflb rfla gndr gndr rfout vddr senb vddi ifout gndi iflb ifla gndd vddd gndd xin pwdnb auxout 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 4 5 6 7 1 2 3 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gndi iflb ifla gndd vddd gndd xin gndr sdata sclk senb vddi ifout gndi gndr rfld rflc gndr rflb rfla gndr gndr gndr rfout vddr auxout pwdnb gndd
si4133g 2 rev. 1.1
si4133g rev. 1.1 3 t able of c ontents section page electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 setting the vco center frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 self-tuning algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 output frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 pll loop dynamics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 rf and if outputs (rfout and ifout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 reference frequency amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power down modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 auxiliary output (auxout) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 pin descriptions: si4133g-bt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 pin descriptions: si4133g-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 si4133g derivative devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 package outline: si4133g-bt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 package outline: si4133g-bm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 contact information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2
si4133g 4 rev. 1.1 electrical specifications table 1. recommended operating conditions parameter symbol test condition min typ max unit ambient temperature t a ?20 25 85 c supply voltage v dd 2.7 3.0 3.6 v supply voltages difference v ? (v ddr ? v ddd ), (v ddi ? v ddd ) ?0.3 ? 0.3 v note: all minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. typical values apply at 3.0 v and an operating temperature of 25c unless otherwise stated. table 2. absolute maximum ratings 1,2 parameter symbol value unit dc supply voltage v dd ?0.5 to 4.0 v input current 3 i in 10 ma input voltage 3 v in ?0.3 to v dd +0.3 v storage temperature range t stg ?55 to 150 o c notes: 1. permanent device damage may occur if the above absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. this device is a high performance rf integrated circuit with an esd rating of < 2 kv. handling and assembly of this device should only be done at esd-protected workstations. 3. for signals sclk, sdata, senb, pwdnb and xin.
si4133g rev. 1.1 5 table 3. dc characteristics (v dd = 2.7 to 3.6 v, t a = ?20 to 85c parameter symbol test condition min typ max unit typical supply current 1 rf1 and if operating ? 18 31 ma rf1 mode supply current 1 ?1317ma rf2 mode supply current 1 ?1217ma if mode supply current 1 ?1014ma standby current pwdnb = 0 ? 1 ? a high level input voltage 2 v ih 0.7 v dd ??v low level input voltage 2 v il ??0.3 v dd v high level input current 2 i ih v ih = 3.6 v, v dd = 3.6 v ?10 ? 10 a low level input current 2 i il v il = 0v, v dd = 3.6 v ?10 ? 10 a high level output voltage 3 v oh i oh = ?500 a v dd ?0.4 ? ? v low level output voltage 3 v ol i oh = 500 a ? ? 0.4 v notes: 1. rf1 = 1.55 ghz, rf2 = 1.2 ghz, if = 800 mhz 2. for signals sclk, sdata, senb, and pwdnb. 3. for signal auxout.
si4133g 6 rev. 1.1 figure 1. sclk timing diagram table 4. serial interface timing (v dd = 2.7 to 3.6 v, t a = ?20 to 85c) parameter 1 symbol test condition min typ max unit sclk cycle time t clk figure 1 40 ? ? ns sclk rise time t r figure 1 ? ? 50 ns sclk fall time t f figure 1 ? ? 50 ns sclk high time t h figure 1 10 ? ? ns sclk low time t l figure 1 10 ? ? ns sdata setup time to sclk 2 t su figure 2 5 ? ? ns sdata hold time from sclk 2 t hold figure 2 0 ? ? ns senb to sclk delay time 2 t en1 figure 2 10 ? ? ns sclk to senb delay time 2 t en2 figure 2 12 ? ? ns senb to sclk delay time 2 t en3 figure 2 12 ? ? ns senb pulse width t w figure 2 10 ? ? ns notes: 1. all timing is referenced to the 50% level of the waveform, unless otherwise noted. 2. timing is not referenced to 50% level of waveform. see figure 2. sclk 80% 20% 50% t r t f t l t clk t h
si4133g rev. 1.1 7 figure 2. serial interface timing diagram figure 3. serial word format d17 d16 d15 a1 a0 t su t en1 t hold t w t en2 t en3 sclk sdata senb d 17 d 16 d 15 d 14 d 13 d 12 d 11 d 10 d 9 d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 a 3 a 2 a 1 a 0 data field address field first bit clocked in last bit clocked in
si4133g 8 rev. 1.1 table 5. rf and if synthesizer characteristics (v dd = 2.7 to 3.6 v, t a = ?20 to 85c) parameter 1 symbol test condition min typ max unit xin input frequency f ref ?13?mhz reference amplifier sensitivity v ref 0.5 ? v dd +0.3 v pp phase detector update frequency f f = f ref /r 200 khz rf1 center frequency range f cen 947 ? 1720 mhz rf2 center frequency range f cen 789 ? 1429 mhz if vco center frequency f cen 526 ? 952 mhz tuning range from f cen note: l ext 10% ?5 ? 5 % rf1 vco pushing open loop ? 0.5 ? mhz/v rf2 vco pushing ? 0.4 ? mhz/v if vco pushing ? 0.3 ? mhz/v rf1 vco pulling vswr = 2:1, all phases, open loop ?0.4?mhz pp rf2 vco pulling ? 0.1 ? mhz pp if vco pulling ? 0.1 ? mhz pp rf1 phase noise 1 mhz offset ? ?132 ? dbc/hz 3 mhz offset ? ?142 ? dbc/hz rf1 integrated phase error 100 hz to 100 khz ? 0.9 ? deg rms rf2 phase noise 1 mhz offset ? ?134 ? dbc/hz 3 mhz offset ? ?144 ? dbc/hz rf2 integrated phase error 100 hz to 100 khz ? 0.7 ? deg rms if phase noise 100 khz offset ? ?117 ? dbc/hz if integrated phase error 100 hz to 100 khz ? 0.4 ? deg rms rf1 harmonic suppression second harmonic ? ?26 ? dbc rf2 harmonic suppression ? ?26 ? dbc if harmonic suppression ? ?26 ? dbc rfout power level z l = 50 ? ?7 ?2 1 dbm ifout power level z l = 50 ? ?8 ?6 ?1 dbm rf1 reference spurs offset = 200 khz ? ?70 ? dbc offset = 400 khz ? ?75 ? dbc offset = 600 khz ? ?80 ? dbc r f2 reference spurs offset = 200 khz ? ?75 ? dbc offset = 400 khz ? ?80 ? dbc offset = 600 khz ? ?80 ? dbc power up request to synthesizer ready time, rf1, rf2, if 2 t pup figures 4, 5 ? 140 ? s power down request to synthesizer off time 3 t pdn figures 4, 5 ? ? 100 ns notes: 1. rf1 = 1.55 ghz, rf2 = 1.2 ghz, if = 550 mhz for all parameters unless otherwise noted. 2. from power up request (pwdnb or senb during a write of 1 to bits pdib and pdrb in register 2) to rf and if synthesizers ready (settled to within 0.1 ppm frequency error). typical settling time to 5 degrees phase error is 120 s. 3. from power down request (pwdnb , or senb during a write of 0 to bits pdib and pdrb in register 2) to supply current equal to i pwdn .
si4133g rev. 1.1 9 figure 4. software power management timing diagram figure 5. hardware power management timing diagram pd ib = 0 pd rb = 0 pd ib = 1 pd rb = 1 t pup t pdn i t i pw dn senb sdata rf and if synthesizers s ettled to w ithin 0.1 ppm frequency error. t pup t pdn i t i pw dn pwdnb rf and if synthesizers settled to within 0.1 ppm frequency error.
si4133g 10 rev. 1.1 figure 6. typical transient response rf1 at 1.6 ghz with 200 khz phase detector update frequency a offset trace a: ch1 fm gate time 133.59375 us 800 hz real 160 hz /div -800 hz axis is 0.1 ppm/div start: 0 s stop: 299.21875 us
si4133g rev. 1.1 11 figure 7. typical rf1 phase noise at 1.6 ghz with 200 khz phase detector update frequency figure 8. typical rf1 spurious response at 1.6 ghz with 200 khz phase detector update frequency 10 2 10 3 10 4 10 5 10 6 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ?60 offset frequency (hz) phase noise (dbc/hz)
si4133g 12 rev. 1.1 figure 9. typical rf2 phase noise at 1.2 ghz with 200 khz phase detector update frequency figure 10. typical rf2 spurious response at 1.2 ghz with 200 khz phase detector update frequency 10 2 10 3 10 4 10 5 10 6 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 ? 60 offset frequency (hz) phase noise (dbc/hz)
si4133g rev. 1.1 13 figure 11. typical if phase noise at 550 mhz with 200 khz phase detector update frequency figure 12. if spurious response at 550 mhz with 200 khz phase detector update frequency 10 2 10 3 10 4 10 5 10 6 ? 150 ? 140 ? 130 ? 120 ? 110 ? 100 ? 90 ? 80 ? 70 offset frequency (hz) phase noise (dbc/hz)
si4133g 14 rev. 1.1 figure 13. typical application circuit: si4133g-bt figure 14. typical application circuit: si4133g-bm sclk sdata gndr rfld rflc gndr rflb rfla gndr gndr rfout vddr senb vddi ifo ut gndi iflb ifla gndd vddd gndd xin pwdnb auxout 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 si4133g-bt rfout 560pf 2nh printed trace inductor or chip inductor printed trace inductors ifo ut 560pf 10nh auxout external clock 560 pf from system controller 0.022 f v dd 0.022 f v dd 0.022 f v dd pdwnb 4 5 6 7 1 2 3 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 si4133g-bm gndi iflb ifla gndd vddd gndd xin gndr rfld rflc gndr rflb rfla gndr external clock from system controller v dd v dd v dd ifout auxout rfout 0.022 f 0.022 f 0.022 f printed trace inductor or chip inductor printed trace inductors 560pf 560pf 10nh 2nh 560pf gndr gndr rfout vddr auxout pwdnb gndd gndr gndr rfout vddr auxout pwdnb gndd gndr gndr rfout vddr auxout pwdnb gndd gndr sdata sclk senb vddi ifout gndi pwdnb
si4133g rev. 1.1 15 functional description the si4133g is a monolithic integrated circuit that performs if and dual-band rf synthesis for many wireless applications such as gsm, dcs1800, and pcs1900. its fast transient response also makes the si4133g especially well suited to gprs and hscsd multislot applications where channel switching and settling times are critical. this integrated circuit (ic), with a minimum number of external components, is all that is necessary to implement the frequency synthesis function. the si4133g has three complete phase-locked loops (plls) with integrated voltage-controlled oscillators (vcos). the low phase noise of the vcos makes the si4133g suitable for use in demanding wireless communications applications. also integrated are phase detectors, loop filters, and reference dividers. the ic is programmed through a three-wire serial interface. one pll is provided for if synthesis, and two plls are provided for dual-band rf synthesis. one rf vco is optimized to have its center frequency set between 947 mhz and 1720 mhz, while the second rf vco is optimized to have its center frequency set between 789 mhz and 1429 mhz. the if vco is optimized to have its center frequency set between 526 mhz and 952 mhz. each pll can adjust its output frequency by 5% relative to its vco center frequency. the center frequency of each of the three vcos is set by connection of an external inductance. inaccuracies in the value of the inductance are compensated for by the si4133g?s proprietary self-tuning algorithm. this algorithm is initiated each time the pll is powered-up (by either the pwdnb pin or by software) and/or each time a new output frequency is programmed. the two rf plls share a common output pin, so only one pll is active at a given time. because the two vcos can be set to have widely separated center frequencies, the rf output can be programmed to service different frequency bands, thus making the si4133g ideal for use in dual-band cellular handsets. the unique pll architecture used in the si4133g produces a transient response that is superior in speed to fractional-n architectures without suffering the high phase noise or spurious modulation effects often associated with those designs. serial interface a timing diagram for the serial interface is shown in figure 2 on page 7. figure 3 on page 7 shows the format of the serial word. the si4133g is programmed serially with 22-bit words comprised of 18-bit data fields and 4-bit address fields. when the serial interface is enabled (i.e., when senb is low) data and address bits on the sdata pin are clocked into an internal shift register on the rising edge of sclk. data in the shift register is then transferred on the rising edge of senb into the internal data register addressed in the address field. the serial interface is disabled when senb is high. table 10 on page 20 summarizes the data register functions and addresses. the internal shift register will ignore any leading bits before the 22 required bits. setting the vco center frequencies the plls can adjust the if and rf output frequencies 5% with respect to their vco center frequencies. each center frequency is established by the value of an external inductance connected to the respective vco. manufacturing tolerances of 10% for the external inductances are acceptable. the si4133g will compensate for inaccuracies in each inductance by executing a self-tuning algorithm following pll power- up or following a change in the programmed output frequency. because the total tank inductance is in the low nh range, the inductance of the package needs to be considered in determining the correct external inductance. the total inductance (l tot ) presented to each vco is the sum of the external inductance (l ext ) and the package inductance (l pkg ). each vco has a nominal capacitance (c nom ) in parallel with the total inductance, and the center frequency is as follows: or tables 6 and 7 summarize these characteristics for each vco. f cen 1 2 l tot c nom ? --------------------------------------------- = f cen 1 2 l pkg l ext + () c nom ? ---------------------------------------------------------------------- =
si4133g 16 rev. 1.1 figure 15. external inductance connection as a design example, suppose it is desired to synthesize frequencies in a 25 mhz band between 1120 mhz and 1145 mhz. the center frequency should be defined as midway between the two extremes, or 1132.5 mhz. the pll will be able to adjust the vco output frequency 5% of the center frequency, or 56.6 mhz of 1132.5 mhz (i.e., from approximately 1076 mhz to 1189 mhz, more than enough for this example). the rf2 vco has a c nom of 4.8 pf, and a 4.1 nh inductance (correct to two digits) in parallel with this capacitance will yield the desired center frequency. an external inductance of 1.8 nh should be connected between rflc and rfld as shown in figure 15. this, in addition to 2.3 nh of l pkg (si4133g-bt), will present the correct total inductance to the vco. in manufacturing, the external inductance can vary 10% of its nominal value and the si4133g will correct for the variation with the self-tuning algorithm. in most cases, particularly for the rf vcos, the requisite value of the external inductance is small enough to allow a pc board trace to be utilized. during initial board layout, a length of trace approximating the desired inductance can be used. for more information, please refer to application note 31. self-tuning algorithm the self-tuning algorithm is initiated immediately following power-up of a pll or, if the pll is already powered, following a change in its programmed output frequency. this algorithm attempts to tune the vco so that its free-running frequency is near the desired output frequency. in so doing, the algorithm will compensate for manufacturing tolerance errors in the value of the external inductance connected to the vco. it will also reduce the frequency error for which the pll must correct to get the precise desired output frequency. the self-tuning algorithm will leave the vco oscillating at a frequency in error by somewhat less than 1% of the desired output frequency. after self-tuning, the pll controls the vco oscillation frequency. the pll will complete frequency locking, eliminating any remaining frequency error. thereafter, it will maintain frequency-lock, compensating for effects caused by temperature and supply voltage variations. the si4133g?s self-tuning algorithm will compensate for component value errors at any temperature within the specified temperature range. however, the ability of the pll to compensate for drift in component values that occur after self-tuning is limited. for external inductances with temperature coefficients around 150 ppm/ o c, the pll will be able to maintain lock for changes in temperature of approximately 30 o c. applications where the pll is regularly powered down (such as gsm) or switched between channels minimize or eliminate the potential effects of temperature drift because the vco is re-tuned when it is powered up or when a new frequency is programmed. in applications where the ambient temperature can drift substantially after self-tuning, it may be necessary to monitor the ldetb (lock-detect bar) signal on the auxout pin to determine the locking state of the pll. (see "auxiliary output (auxout)" on page 18 for how to select ldetb.) the ldetb signal is normally low after self-tuning is completed but will rise to a logic high condition when table 6. si4133g-bt vco characteristics vco fcen range (mhz) cnom (pf) lpkg (nh) lext range (nh) min max min max rf1 947 1720 4.3 2.0 0.0 4.6 rf2 789 1429 4.8 2.3 0.3 6.2 if 526 952 6.5 2.1 2.2 12.0 table 7. si4133g-bm vco characteristics vco fcen range (mhz) cnom (pf) lpkg (nh) lext range (nh) min max min max rf1 947 1720 4.3 1.5 0.5 5.1 rf2 789 1429 4.8 1.5 1.1 7.0 if 526 952 6.5 1.6 2.7 12.5 l pkg 2 l pkg 2 l ext
si4133g rev. 1.1 17 either the if or rf pll nears the limit of its compensation range (ldetb will also be high when either pll is executing the self-tuning algorithm). the output frequency will still be locked when ldetb goes high, but the pll will eventually lose lock if the temperature continues to drift in the same direction. therefore, if ldetb goes high both the if and rf plls should promptly be re-tuned by initiating the self-tuning algorithm. output frequencies the if and rf output frequencies are set by programming the n-divider registers. each rf pll has its own n register and can be programmed independently. all three pll r dividers are fixed at r = 65 to yield a 200 khz phase detector update rate from a 13 mhz reference frequency. programming the n-divider register for either rf1 or rf2 automatically selects the associated output. the reference frequency on the xin pin is divided by r and this signal is the input to the pll?s phase detector. the other input to the phase detector is the pll?s vco output frequency divided by n. the pll works to make these frequencies equal. that is, after an initial transient or for xin = 13 mhz this simplifies to the integer n is set by programming the rf1 n-divider register (register 3), the rf2 n-divider register (register 4), and the if n-divider register (register 5). each n divider is implemented as a conventional high speed divider. that is, it consists of a dual-modulus prescaler, a swallow counter, and a lower speed synchronous counter. however, the calculation of these values is done automatically. only the appropriate n value needs to be programmed. pll loop dynamics the transient response for each pll has been optimized for a gsm application. vco gain, phase detector gain, and loop filter characteristics are not programmable. the settling time for each pll is directly proportional to its phase detector update period t (t equals 1/f ). for a gsm application with a 13 mhz reference frequency, the rf and if plls t =5 s. during the first 6.5 update periods, the si4133g executes the self-tuning algorithm. thereafter the pll controls the output frequency. because of the unique architecture of the si4133g plls, the time required to settle the output frequency to 0.1 ppm error is approximately 21 update periods. thus, the total time after power-up or a change in programmed frequency until the synthesized frequency is well settled (including time for self-tuning) is around 28 update periods or 140 s. rf and if outputs (rfout and ifout) the rfout pin is driven by an amplifier that buffers the output pin from the rf vcos, and must be coupled to its load through an ac coupling capacitor. the amplifier receives its input from either the rf1 or rf2 vco, depending upon which n-divider register was last written. for example, programming the n-divider register for rf1 automatically selects the rf1 vco output. a matching network is required to maximize power delivered into a 50 ? load. the network consists of a 2 nh series inductance, which may be realized with a pc board trace, connected between the rfout pin and the ac coupling capacitor. the network is made to provide an adequate match for both the rf1 and rf2 frequency bands, and also filters the output signal to reduce harmonic distortion. a 50 ? load is not required for proper operation of the si4133g. depending on transceiver requirements, the matching network may not be needed. see figure 16. figure 16. rfout 50 ? ? ? ? test circuit the ifout pin is driven by an amplifier that buffers the output pin from the if vco. the ifout pin must be coupled to its load through an ac coupling capacitor. a matching network is required to maximize power delivered into a 50 ? load. see figure 17. f out n ----------- - f ref 65 ----------- = f out n 65 ------ f ref ? = f out n 200 khz ? = rfout 2 nh 560 pf 50 ?
si4133g 18 rev. 1.1 figure 17. ifout 50 ? ? ? ? test circuit the if output level is dependent upon the load. figure 18 displays the output level versus load resistance for a variety of output frequencies. figure 18. typical if output voltage vs. load resistance at 550 mhz for resistive loads greater than 500 ? the output level saturates and the bias currents in the if output amplifier are higher than they need be. the lpwr bit in the main configuration register (register 0) can be set to 1 to reduce the bias currents and therefore reduce the power dissipated by the if amplifier. for loads less than 500 ? lpwr should be set to 0 to maximize the output level. reference frequency amplifier the si4133g provides a reference frequency amplifier. if the driving signal has cmos levels it can be connected directly to the xin pin. otherwise, the reference frequency signal should be ac coupled to the xin pin through a 560 pf capacitor. power down modes table 9 summarizes the power down functionality. the si4133g can be powered down by taking the pwdnb pin low or by setting bits in the power down register (register 1). when the pwdnb pin is low, the si4133g will be powered down regardless of the power down register settings. when the pwdnb pin is high, power management is under control of the power down register bits. the reference frequency amplifier, if, and rf sections of the si4133g circuitry can be individually powered down by setting the power down register bits pdib and pdrb low, respectively. the reference frequency amplifier will also be powered up if either of the pdrb or pdib bits are high. also, setting the autopdb bit to 1 in the main configuration register (register 0) is equivalent to setting both bits in the power down register to 1. the serial interface remains available and can be written in all power down modes. auxiliary output (auxout) the signal appearing on auxout is selected by setting the auxsel bits in the main configuration register (register 0). the ldetb signal can be selected by setting the auxsel bits to 11. as discussed previously, this signal can be used to indicate that the if or rf pll is about to lose lock due to excessive ambient temperature drift and should be re-tuned. table 8. l match values frequency l match 500?600 mhz 40 nh 600?800 mhz 27 nh 800?1 ghz 18 nh ifout l match 560 pf 50 ? 0 50 100 150 200 250 300 350 400 450 0 200 400 600 800 1000 1200 load resistance ( ? ? ? ? ) output voltage (mvrms ) lpwr=0 lpwr=1
si4133g rev. 1.1 19 table 9. power down configuration pwdnb pin autopdb pdib pdrb if circuitry rf circuitry pwdnb = 0 xxxoffoff pwdnb = 1 000offoff 001offon 010onoff 011onon 1xxonon
si4133g 20 rev. 1.1 control registers note: registers 1 and 6?15 are reserved. writes to these registers may result in unpredictable behavior. any register not listed here is reserved and should not be written. table 10. register summary register name bit 17 bit 16 bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0main configuration 0000 auxsel [1:0] 000000 lpwr 0 auto pdb 010 1 reserved 2 power down0000000000000000 pdib pdrb 3rf1 n divider n rf1 [17:0] 4rf2 n divider0 n rf [16:0] 5if n divider00 n if [15:0] 6 reserved . . . 15 reserved
si4133g rev. 1.1 21 register 0. main configuration address field = a[3:0] = 0000 bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 0000auxsel [1:0] 0 0 0000 lpwr 0 auto pdb 010 bit name function 17:14 reserved program to zero. 13:12 auxsel [1:0] auxiliary output pin definition. 00 = reserved. 01 = force output low. 10 = reserved. 11 = lock detect?ldetb. 11:6 reserved program to zero. 5lpwr output power-level settings for if synthesizer circuit. 0 = r load < 500 ? ?normal power mode. 1 = r load 500 ? ?low power mode. 4 reserved program to zero. 3 autopdb auto power down 0 = software powerdown is controlled by register 2. 1 = equivalent to setting all bits in register 2 = 1. 2 reserved program to zero. 1 reserved program to one . 0 reserved program to zero.
si4133g 22 rev. 1.1 register 2. power down address field (a[3:0]) = 0010 bit d17 d16 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 name 000000000000000 0 pdib pdrb bit name function 17:2 reserved program to zero. 1pdib power down if synthesizer. 0 = if synthesizer powered down. 1 = if synthesizer on. note: always program to 0 for si4113g. 0 pdrb power down rf synthesizer. 0 = rf synthesizer powered down. 1 = rf synthesizer on. note: always program to 0 for si4112g. register 3. rf1 n divider address field (a[3:0]) = 0011 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name n rf1 [17:0] bit name function 17:0 n rf1 [17:0] n divider for rf1 synthesizer. register reserved for si4112g, si4122g. writes to this register may result in unpre- dictable behavior.
si4133g rev. 1.1 23 register 4. rf2 n divider address field = a[3:0] = 0100 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 0n rf2 [16:0] bit name function 17 reserved program to zero. 16:0 n rf2 [16:0] n divider for rf2 synthesizer. register reserved for si4112g, si4123g. writes to this register may result in unpredictable behavior. register 5. if n divider address field (a[3:0]) = 0101 bit d17d16d15d14d13d12d11d10d9d8d7d6d5d4d3d2d1d0 name 00 n if [15:0] bit name function 17:16 reserved program to zero. 15:0 n if [15:0] n divider for if synthesizer. register reserved for si4113g. writes to this register may result in unpredictable behavior.
si4133g 24 rev. 1.1 pin descriptions: si4133g-bt pin number(s) name description 1 sclk serial clock input 2 sdata serial data input 3, 6, 9, 10 gndr common ground for rf analog circuitry 4, 5 rflc, rfld pins for inductor connection to rf2 vco 7, 8 rfla, rflb pins for inductor connection to rf1 vco 11 rfout radio frequency (rf) output of the selected rf vco 12 vddr supply voltage for the rf analog circuitry 13 auxout auxiliary output 14 pwdnb power down input pin 15 xin reference frequency amplifier input 16, 18 gndd common ground for digital circuitry 17 vddd supply voltage for digital circuitry 19, 20 ifla, iflb pins for inductor connection to if vco 21 gndi common ground for if analog circuitry 22 ifout intermediate frequency (if) output of the if vco 23 vddi supply voltage for if analog circuitry 24 senb enable serial port input sclk sdata gndr rfld rflc gndr rflb rfla gndr gndr rfout vddr senb vddi ifout gndi iflb ifla gndd vddd gndd xin pwdnb auxout 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13
si4133g rev. 1.1 25 table 11. pin descriptions for si4133g derivatives?tssop pin number si4133g-bt si4123g-bt si4122g-bt si4113g-bt si4112g-bt 1 sclk sclk sclk sclk sclk 2 sdata sdata sdata sdata sdata 3 gndr gndr gndr gndr gndd 4 rfld gndr rfld rfld gndd 5 rflc gndr rflc rflc gndd 6 gndr gndr gndr gndr gndd 7 rflb rflb gndr rflb gndd 8 rfla rfla gndr rfla gndd 9 gndr gndr gndr gndr gndd 10 gndr gndr gndr gndr gndd 11 rfout rfout rfout rfout gndd 12 vddr vddr vddr vddr vddd 13 auxout auxout auxout auxout auxout 14 pwdnb pwdnb pwdnb pwdnb pwdnb 15 xin xin xin xin xin 16 gndd gndd gndd gndd gndd 17 vddd vddd vddd vddd vddd 18 gndd gndd gndd gndd gndd 19 ifla ifla ifla gndd ifla 20 iflb iflb iflb gndd iflb 21 gndi gndi gndi gndd gndi 22 ifout ifout ifout gndd ifout 23 vddi vddi vddi vddd vddi 24 senb senb senb senb senb
si4133g 26 rev. 1.1 pin descriptions: si4133g-bm pin number(s) name description 1, 4, 7?9, 28 gndr common ground for rf analog circuitry 2, 3 rflc, rfld pins for inductor connection to rf2 vco 5,6 rfla, rflb pins for inductor connection to rf1 vco 10 rfout radio frequency (rf) output of the selected rf vco 11 vddr supply voltage for the rf analog circuitry 12 auxout auxiliary output 13 pwdnb power down input pin 14, 16, 18 gndd common ground for digital circuitry 15 xin reference frequency amplifier input 17 vddd supply voltage for digital circuitry 19, 20 ifla, iflb pins for inductor connection to if vco 21, 22 gndi common ground for if analog circuitry 23 ifout intermediate frequency (if) output of the if vco 24 vddi supply voltage for if analog circuitry 25 senb enable serial port input 26 sclk serial clock input 27 sdata serial data input 4 5 6 7 1 2 3 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 gndi iflb ifla gndd vddd gndd xin gndr sdata sclk senb vddi ifo ut gndi gndr rfld rflc gndr rflb rfla gndr gndr gndr rfout vddr auxout pwdnb gndd
si4133g rev. 1.1 27 table 12. pin descriptions for si4133g derivatives?mlp pin number si4133g-bm si4123g-bm si4122g-bm SI4113G-BM si4112g-bm 1 gndr gndr gndr gndr gndd 2 rfld gndr rfld rfld gndd 3 rflc gndr rflc rflc gndd 4 gndr gndr gndr gndr gndd 5 rflb rflb gndr rflb gndd 6 rfla rfla gndr rfla gndd 7 gndr gndr gndr gndr gndd 8 gndr gndr gndr gndr gndd 9 gndr gndr gndr gndr gndd 10 rfout rfout rfout rfout gndd 11 vddr vddr vddr vddr vddd 12 auxout auxout auxout auxout auxout 13 pwdnb pwdnb pwdnb pwdnb pwdnb 14 gndd gndd gndd gndd gndd 15 xin xin xin xin xin 16 gndd gndd gndd gndd gndd 17 vddd vddd vddd vddd vddd 18 gndd gndd gndd gndd gndd 19 ifla ifla ifla gndd ifla 20 iflb iflb iflb gndd iflb 21 gndi gndi gndi gndd gndi 22 gndi gndi gndi gndd gndi 23 ifout ifout ifout gndd ifout 24 vddi vddi vddi vddd vddi 25 senb senb senb senb senb 26 sclk sclk sclk sclk sclk 27 sdata sdata sdata sdata sdata 28 gndr gndr gndr gndr gndd
si4133g 28 rev. 1.1 ordering guide si4133g derivative devices the si4133g performs both if and dual-band rf frequency synthesis. the si4112g, si4113g, si4122g, and the si4123g are derivatives of this device. table 13 outlines which synthesizers each derivative device features as well as which pins and registers coincide with each synthesizer. ordering part number description operating temperature si4133g-bt* si4133g-bm rf1/rf2/if ?20 to 85 o c si4123g-bt* si4123g-bm rf1/if ?20 to 85 o c si4122g-bt* si4122g-bm rf2/if ?20 to 85 o c si4113g-bt* SI4113G-BM rf1/rf2 ?20 to 85 o c si4112g-bt* si4112g-bm if ?20 to 85 o c *note: tssop not recommended for new designs. table 13. si4133g derivatives name synthesizer pins registers si4112g if ifla, iflb n if , r if , pdib, ifdiv, lpwr, autopdb = 0, pdrb = 0 si4113g rf1, rf2 rfla, rflb, rflc, rfld n rf1 , n rf2 , r rf1 , r rf2 , pdrb, autopdb = 0, pdib = 0 si4122g rf2, if rflc, rfld, ifla, iflb n rf2 , r rf2 , pdrb, n if , r if , pdib, lpwr si4123g rf1, if rfla, rflb, ifla, iflb n rf1 , r rf1 , pdrb, n if , r if , pdib, lpwr si4133g rf1, rf2, if rfla, rflb, rflc, rfld, ifla, iflb n rf1 , n rf2 , r rf1 , r rf2 , pdrb, n if , r if , pdib, lpwr
si4133g rev. 1.1 29 package outline: si4133g-bt figure 19. 24-pin thin small shrink outline package (tssop) table 14. package diagram dimensions symbol millimeters min nom max a ? 1.10 1.20 a1 0.05 ? 0.15 a2 0.80 1.00 1.05 b0.19 ?0.30 c0.09?0.20 d 7.70 7.80 7.90 e0.65 bsc e6.40 bsc e1 4.30 4.40 4.50 l 0.45 0.60 0.75 l1 1.00 ref r0.09 ? ? r1 0.09 ? ? s0.20 ? ? 10 ?8 2 12 ref 3 12 ref l 1 l1 s r1 r 2 3 c d a1 a a2 b e1 e e
si4133g 30 rev. 1.1 package outline: si4133g-bm figure 20. 28-pin micro leadframe package (mlp) table 15. package dimensions controlling dimension: mm symbol millimeters min nom max a ? 0.90 1.00 a1 0.00 0.01 0.05 b 0.18 0.23 0.30 d5.00 bsc d1 4.75 bsc e5.00 bsc e1 4.75 bsc n28 nd 7 ne 7 e0.50 bsc l 0.50 0.60 0.75 12
si4133g rev. 1.1 31 n otes :
si4133g 32 rev. 1.1 contact information silicon laboratories inc. 4635 boston lane austin, texas 78735 tel:1+ (512) 416-8500 fax:1+ (512) 416-9669 toll free:1+ (877) 444-3032 email: productinfo@silabs.com internet: www.silabs.com silicon laboratories and silicon labs are trademarks of silicon laboratories inc. other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders. the information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. silicon laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resu lting from the use of information included herein. additionally, silicon laboratories assumes no responsibility for the functioning of und escribed fea- tures or parameters. silicon laboratories reserves the right to make changes without further notice. silicon laboratories makes no war- ranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does silicon labor atories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability , including without limitation consequential or incidental damages. silicon laboratories products are not designed, intended, or authorized for use in applica- tions intended to support or sustain life, or for any other application in which the failure of the silicon laboratories produc t could create a situation where personal injury or death may occur. should buyer purchase or use silicon laboratories products for any such uni ntended or unauthorized application, buyer shall indemnify and hold silicon laboratories harmless against all claims and damages.

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